library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_type.all;

entity filtre_top is 
   port(
	   clock_50_M : in std_logic;
		dac_clock : out std_logic;
		dac_write : out std_logic;
		dac_mode : out std_logic;
		symbol_clock : out std_logic;
		dac_data : out integer range 0 to 16383
	);
end;

architecture structural of filtre_top is

   signal bit_clock : std_logic;
	signal bit_data : std_logic;
	signal sample_clock : std_logic;
	signal bit_couple : unsigned(1 downto 0);
	signal I : integer range -1 to 1;
	signal I_oversampled : integer range -1 to 1 ;
	signal I_filtered : integer range -8192 to 8191;
	
begin

	module1 : entity work.gen_horloge generic map(FREQ => freq_10_MHz) port map(clock => clock_50_M, pulse => sample_clock);
	
	module2 : entity work.div_freq_by_2 port map(clock => sample_clock, clock_divided => bit_clock);
	
	module2bis : entity work.div_freq_by_2 port map(clock => bit_clock, clock_divided => symbol_clock);
	
	module3 : entity work.gen_binaire port map(clock => clock_50_M, register_output => bit_data);
	
	module4 : entity work.serial_2_parallel port map(serial_bit => bit_data, clock => bit_clock, parallel_bit => bit_couple);
	
	module5 : entity work.mapping port map(bit_couple => bit_couple,I => I);
	
	module6 : entity work.oversampling port map(clock_sample => sample_clock, symbol => I, symbol_oversampled => I_oversampled);
	
	module7 : entity work.filtrage port map(clock => sample_clock, x0 => I_oversampled, y => I_filtered);
	
	module8 : entity work.scaling port map(centered_y => I_filtered, positive_y => dac_data);	
	
	dac_write <= sample_clock;
	
	dac_clock <= sample_clock;
	
	dac_mode <= '1';
	
end;