# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other 
# applicable license agreement, including, without limitation, 
# that your use is for the sole purpose of programming logic 
# devices manufactured by Altera and sold by Altera or its 
# authorized distributors.  Please refer to the applicable 
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
# Date created = 10:02:10  April 27, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		filtre_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC5C6F27C7
set_global_assignment -name TOP_LEVEL_ENTITY filtre_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:02:10  APRIL 27, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name VHDL_FILE gen_binaire.vhd
set_global_assignment -name VHDL_FILE serial_2_parallel.vhd
set_global_assignment -name VHDL_FILE gen_horloge.vhd
set_global_assignment -name VHDL_FILE mapping.vhd
set_global_assignment -name VHDL_FILE oversampling.vhd
set_global_assignment -name VHDL_FILE filtrage.vhd
set_global_assignment -name VHDL_FILE filtre_top.vhd
set_global_assignment -name VHDL_FILE scaling.vhd
set_global_assignment -name VHDL_FILE simulation/modelsim/gen_binaire_tb.vhd
set_global_assignment -name VHDL_FILE simulation/modelsim/serial_2_parallel_tb.vhd
set_global_assignment -name VHDL_FILE simulation/modelsim/gen_horloge_tb.vhd
set_global_assignment -name VHDL_FILE simulation/modelsim/mapping_tb.vhd
set_global_assignment -name VHDL_FILE simulation/modelsim/oversamplng_tb.vhd
set_global_assignment -name VHDL_FILE simulation/modelsim/filtrage_tb.vhd
set_global_assignment -name VHDL_FILE simulation/modelsim/scaling_tb.vhd
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH filtre_top -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME gen_binaire -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME dut -section_id gen_binaire
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id gen_binaire
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME gen_binaire_tb -section_id gen_binaire
set_global_assignment -name EDA_TEST_BENCH_NAME serial_2_parallel -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME dut -section_id serial_2_parallel
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id serial_2_parallel
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME serial_2_parallel_tb -section_id serial_2_parallel
set_global_assignment -name EDA_TEST_BENCH_NAME mapping -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id mapping
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id mapping
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME mapping_tb -section_id mapping
set_global_assignment -name VHDL_FILE simulation/modelsim/mapping_tb_better.vhd
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name EDA_TEST_BENCH_NAME mapping_better -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME dut -section_id mapping_better
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id mapping_better
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME mapping_tb_better -section_id mapping_better
set_global_assignment -name EDA_TEST_BENCH_NAME gen_horloge -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id gen_horloge
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id gen_horloge
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME gen_horloge_tb -section_id gen_horloge
set_global_assignment -name EDA_TEST_BENCH_NAME filtrage -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id filtrage
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id filtrage
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME filtrage_tb -section_id filtrage
set_global_assignment -name EDA_TEST_BENCH_NAME scaling -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id scaling
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id scaling
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME scaling_tb -section_id scaling
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity C5G_Default -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity C5G_Default -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -entity C5G_Default -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity C5G_Default -section_id Top
set_global_assignment -name VHDL_FILE simulation/modelsim/filtre_top_tb.vhd
set_global_assignment -name EDA_TEST_BENCH_NAME filtre_top -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id filtre_top
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 ms" -section_id filtre_top
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME filtre_top_tb -section_id filtre_top
set_location_assignment PIN_R20 -to clock_50_M
set_location_assignment PIN_C15 -to dac_data[13]
set_location_assignment PIN_B15 -to dac_data[12]
set_location_assignment PIN_B19 -to dac_data[11]
set_location_assignment PIN_C20 -to dac_data[10]
set_location_assignment PIN_A11 -to dac_data[9]
set_location_assignment PIN_B10 -to dac_data[8]
set_location_assignment PIN_B11 -to dac_data[7]
set_location_assignment PIN_A12 -to dac_data[6]
set_location_assignment PIN_C10 -to dac_data[5]
set_location_assignment PIN_D10 -to dac_data[4]
set_location_assignment PIN_B9 -to dac_data[3]
set_location_assignment PIN_C9 -to dac_data[2]
set_location_assignment PIN_E11 -to dac_data[1]
set_location_assignment PIN_E10 -to dac_data[0]
set_location_assignment PIN_A21 -to dac_mode
set_location_assignment PIN_B22 -to dac_write
set_location_assignment PIN_A18 -to dac_clock
set_global_assignment -name VHDL_FILE counter_14_bits.vhd
set_global_assignment -name VHDL_FILE test_dac_top.vhd
set_global_assignment -name VHDL_FILE simulation/modelsim/test_dac_top_tb.vhd
set_global_assignment -name EDA_TEST_BENCH_NAME test_dac_top -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_dac_top
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id test_dac_top
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_dac_top_tb -section_id test_dac_top
set_global_assignment -name VHDL_FILE div_freq_by_2.vhd
set_global_assignment -name VHDL_FILE simulation/modelsim/div_freq_by_2_tb.vhd
set_global_assignment -name EDA_TEST_BENCH_NAME div_freq_by_2 -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id div_freq_by_2
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 s" -section_id div_freq_by_2
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME div_freq_by_2_tb -section_id div_freq_by_2
set_location_assignment PIN_A19 -to symbol_clock
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/gen_binaire_tb.vhd -section_id gen_binaire
set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/serial_2_parallel_tb.vhd -section_id serial_2_parallel
set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/mapping_tb.vhd -section_id mapping
set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/mapping_tb_better.vhd -section_id mapping_better
set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/gen_horloge_tb.vhd -section_id gen_horloge
set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/filtrage_tb.vhd -section_id filtrage
set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/scaling_tb.vhd -section_id scaling
set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/filtre_top_tb.vhd -section_id filtre_top
set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/test_dac_top_tb.vhd -section_id test_dac_top
set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/div_freq_by_2_tb.vhd -section_id div_freq_by_2
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top